With IC designs using conventional technologies, test structures are added into a functional IC design to improve yields. Several test structures, like the scan chain, the memory built-in self test (BIST)/built-in self repair (BISR) and Joint Test Access Group (JTAG) are simultaneously adopted to improve such yields. Such test structures are run at high frequencies in order to (i) minimize test time and (ii) accurately reveal manufacturing defects.
With the increasing complexity of designs and multi-million gate technology, verifying test structures based on simulation uses a more significant amount of time. The effort in many designs is becoming unmanageable. Recent test methodologies have been greatly enriched to provide more solutions in order to increase yields. Such test methodologies assure silicon quality for customer applications. Static Timing Analysis (STA) has become an effective solution to verify the correct timing implementation of all different test structures adopted. Timing analysis is needed at several stages in the implementation flow to identify design delays. STA evaluates the effects of logic delays or timing constraints. Prior to STA, correct implementation of test structures was verified by simulation.
However, with the increasing complexity of IC designs, performing simulation is not efficient. Simulation needs long CPU times (matter of days) and the debugging is not easy to perform. Such long CPU runs are difficult to manage for the typical engineer since the long CPU runs often lead to a significant increase in Turn Around Time. Static timing analysis is more efficient than performing simulation since a typical verification can take hours (in place of days) and the debugging of timing issues is more straightforward. STA is also more accurate in very deep submicron technologies since important delay effects due to cross-talk or on-chip variation are taken into account. Such effects are very difficult to be emulated in the simulation environment. However, STA fails to provide an automatic solution for simplifying (i) timing constraint generation that corresponds to simulation pattern generation, (ii) STA runs and (iii) timing result analysis.
Silicon vendors often need to develop in-house software. Third party electronic design analysis (EDA) test tool providers also develop additional software. The in-house software comprises proprietary tools which account for specialized tasks needed by particular silicon vendors. An application engineer often needs to write STA scripts from scratch based on (i) personal knowledge of test structures and (ii) the skill level in the scripting language and the PrimeTime® commands. The application engineer is often found “reinventing the wheel”. Such redundancy runs the risk of creating errors which can lead to very expensive silicon redesign. With conventional approaches, the application engineer needs to be continuously updated on various third party EDA test tools such as tools produced by LogicVision®, Mentor®, and Synopsys®. The usage of such EDA test tools in other tools developed also need to be revisited by the typical design engineer.
Timing driven physical optimization tools (i.e., in-house software and third-party test tool providers) need a unique timing constraint setup. With such a unique timing constraint setup, timing constraints for the logic of both the functional design and test structures need to be included. Memory instances are embedded in functional paths, but the memory instances are reached by the memory BIST test logic. Such a condition will lead to overlapping timing constraints (which produce undesired results) or are completely ignored. With such conditions, the final result is not what is expected. Other iterations are needed to fix timing standards that are needed by the overlapping logic in the functional design and in test structures. In order to include all timing constraints for overlapping logic between functional designs and test structures, the user has to merge timing constraints associated with the functional design and the test structures. Such a complex task makes it necessary for a user to acquire (i) a deep knowledge of the timing needs for various test structures and (ii) an understanding of the limits of physical implementation tools. Conventional approaches fail to (i) provide a correct timing constraint setup (which is a key point for obtaining a good physical implementation) and (ii) take into account that constraint merging is more complex than file concatenation.
It would be desirable to provide a method and/or apparatus for the automatic generation of timing constraints for the validation/signoff of test structures.